The present invention is related in general to the field of semiconductor devices and processes, and more specifically to methods for reliably assembling integrated circuit chips directly onto organic substrates.
One of the major trends in semiconductor packaging is the effort to shrink the package outline so that the package consumes less area and less height when it is mounted onto the circuit board. Another powerful trend is the effort to achieve the outline reduction with minimum cost (both material and manufacturing cost). One of the most successful approaches has been the development of so-called xe2x80x9cchip-scale packagesxe2x80x9d. These packages have an outline adding less than 20% to the chip area. A chip-scale package which has only the size of the chip itself, is often referred to as xe2x80x9cchip-size packagexe2x80x9d.
Within the semiconductor memory product families, one of the most promising concepts for chip-scale packages is the so-called xe2x80x9cboard-on-chipxe2x80x9d design. Recently, several patent applications for this design concept have been submitted, entitled xe2x80x9cChip-Size Integrated Circuit Packagexe2x80x9d (Serial # 9702348-5 filed in Singapore on Jul. 2, 1997, and Serial # 08/994,627 filed in the U.S. on Dec. 19. 1997), xe2x80x9cThin Chip-Size Integrated Circuit Package and Method of Fabricationxe2x80x9d (Serial # 9800005-2 and Serial # 9800006-0 filed in Singapore on Jan. 2, 1998), xe2x80x9cSemiconductor Device Testing and Burn-in Methodologyxe2x80x9d (Serial # 9800617-4, filed in Singapore on Mar. 25, 1998, and Serial # 9800654-7, filed in Singapore on Mar. 28, 1998), xe2x80x9cMethod of Encapsulating Thin Semiconductor Chip-Scale Packagesxe2x80x9d (filed in Singapore on Aug. 25, 1998), all assigned to Texas Instruments Incorporated. Progress has been made in reducing the area and height requirements of packages, but frustrating problems still remain in maximizing adhesion, device reliability assurance and manufacturing cost reduction.
The patent disclosure entitled xe2x80x9cApparatus and Method for Direct Silicon Chip Attachment to a Lead Framexe2x80x9d (Serial # 9800171-2 filed in Singapore on Jan. 23, 1998, and Serial # 09/115,160 filed in the U.S. on Jul. 14, 1998), also assigned to Texas Instruments Incorporated, describes a process to fabricate a chip-scale package by attaching a silicon chip to a printed circuit board using a metal layer and an adhesive layer, thus forming a strong attachment. The metal layer may be disposed on the printed circuit board with the adhesive layer disposed between the metal layer and the chip or the metal layer may be disposed on the chip with the adhesive layer disposed between the metal layer and the printed circuit board. Unfortunately, the process of using both and a metal layer and an adhesive layer is expensive.
In the last few years, several publications discussed principal approaches of increasing the adhesion strength. In xe2x80x9cPolyimide Surface Characteristics for Adhesion Strength at the Interface between Polyimide and Mold Resinxe2x80x9d (Proc. IEEE Singapore IPFA, pp. 6-10, 1993), M. Amagai et al. exposed photosensitive and non-photosensitive polyimides to reactive ion etching plasma and then encapsulated the samples in two types of thermoplastic molding resins. The authors demonstrated the advantage of breaking Cxe2x80x94N chemical bonds by the plasma energy, making the polyimide surface very hydrophilic with an increasing density of carbonyl and carboxyl groups. They believed that the polyimide molecules are oriented parallel to the surface and that their free radicals (carbonyl and carboxyl groups) are subsequently oriented perpendicular to the polyimide surface. The results suggested that the interfacial adhesion is due to the chemical bond between the hydrogen of molding resin and the oxygen of the polyimide surface. Furthermore, the authors found that the plasma treatment increases the polyimide surface roughness. Increased contact area improves the interfacial adhesion.
Similar results of adhesion between plasma-exposed polyimide layers and epoxy molding compounds were reported by M. Amagai et al. in xe2x80x9cThe Effect of Polyimide Surface Morphology and Chemistry on Package Cracking Induced by Interfacial Delaminationxe2x80x9d (Proc. IEEE International Reliability Physics Symposium, pp. 101-107, 1994). The use of an epoxy molding resin which had enhanced rotational freedom at the molecular level (non-linear molecule) increased the adhesion and prevented interfacial delamination and package cracking.
The knowledge gained was applied to polyimide-to-metal adhesion in xe2x80x9cThe Effect of Adhesive Surface Chemistry and Morphology on Package Cracking in Tapeless Lead-on-Chip (LOC) Packagesxe2x80x9d (45th IEEE Electronic Components and Technology Conference, 1995). The LOC package is the dominant package type for centerline-bonded memory devices since the 1 Mbit DRAM; today""s 64 and 256 Mbit DRAM are also packaged using the LOC technology. In the so-called xe2x80x9ctapelessxe2x80x9d modification, a thermoplastic adhesive layer, deposited on the protective passivation layer of the chip surface, has replaced the original double-sided adhesive tape. From the standpoint of cost reduction, this is an improvement, but still not a satisfactory solution. M. Amagai""s work focused on the interfacial adhesion strength the epoxy molding compound and the adhesive surface. He found that the strength is primarily determined by the degree of bonding between the hydrogen of the epoxy molding compound and the silicone, oxygen, and fluorine of the adhesive surface. Relatively little attention was given to the adhesion between the metallic leadframe (copper, iron-nickel alloy, etc.) and the adhesive layer.
In modern chip-size packages, the lead-on-chip (LOC) concept has been replaced by the board-on-chip (BOC) concept. Little is known about maximizing the adhesion between the board and the adhesive surface, and no investigation has been performed to maximize adhesion directly between the board and the protective passivation layer of the chip surface. The goal of offering for commercial products a cost-effective, reliable method of manufacturing in high volume and with flexible, low-cost process has remained elusive, until now.
Consequently, an urgent need has arisen for assembling chip-scale semiconductor packages based on simplified, low-cost processes that result in reliable products and at the same time achieve improvements toward the goal of small outline and low profile packages. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, and should allow the usage of various formulations of board materials. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
The present invention provides a method of assembling a semiconductor device; it especially relates to high density, high speed integrated circuits in packages which have an outline similar to the integrated circuit chip itself, and a low profile. These circuits can be found in many device families such as processors, digital and analog devices, memory and logic devices, high frequency and high power devices, especially in large chip area categories. The invention helps to alleviate the space constraints in continually shrinking applications such as cellular communications, pagers, hard disk drives, laptop computers and medical instrumentation.
In accordance with the present invention, an preactivation method is provided for the protective polymer layer on the surface of integrated circuit chips which imparts adhesiveness to the polymer layer. Furthermore, an electrically insulating substrate is provided, comprising a plurality of conductive routing strips integral with the substrate. This substrate is directly attached to the preactivated polymer layer. The preactivation comprises a plasma exposure of the polymer layer for increasing the surface roughness and creating molecular radicals consisting of chemically unsaturated bonds.
It is an object of the present invention to be applicable to a variety of different semiconductor chip-scale package (CSP) designs, for example: Chip attached directly to board, chip assembled to board with interim metal layer, center-line bonding, peripheral bonding, wire bonding, and flip-chip solder bonding.
Another object of the present invention is to provide a low-cost method and system for assembling chip-scale devices in thin overall profile.
Another object of the present invention is to provide higher production throughput.
Another object of the present invention is to improve product quality by adhesion uniformity, and to enhance reliability assurance by controlling mechanical stress, minimizing moisture absorption, and general in-process control at no extra cost.
Another object of the invention is to introduce assembly concepts for thin profiles which are flexible so that they can be applied to many families of semiconductor products, and are general so that they can be applied to several future generations of products.
Another object of the invention is to minimize the cost of capital investment and the movement of parts and product in the equipment.
These objects have been achieved by the teachings of the invention concerning systems and methods suitable for mass production. Various modifications have been employed for the assembly of semiconductor chips and insulating substrates, as well as interconnection techniques.
In one embodiment of the invention, the method of attaching the chip to the organic substrate includes positioning the substrate in contact with the preactivated polymer layer on the chip. The chip can be mounted on a stage where heat is applied to the chip and the substrate. Also, force may be applied between the chip and the substrate. In one embodiment of the invention, the temperature applied to the chip is between 150 and 350xc2x0 C. and may preferably be about 200xc2x0 C. In another embodiment of the invention, the force applied between the chip and the substrate may be between 5 and 7 kg and preferably about 5.5 kg. The force may be applied for between 2 and 10 s and preferably for about 5 s.
In yet another embodiment of the present invention, a metal layer is disposed on the surface of the substrate facing the chip prior to attaching this surface to the preactivated polymer layer on the chip. When heat is applied to the chip and the substrate, the temperature applied may be between 150 and 350xc2x0 C. and may preferably be about 200xc2x0 C. When force is applied between the chip and the substrate, the force may be between about 1.5 and 7.0 kg and preferably be about 3 kg. The force may be applied for between 2 and 10 s and preferably for about 5 s.
In another embodiment of the invention, a transfer molding process replaces conventional encapsulation methods, with the process parameters (temperature, time, pressure, transfer, curing, etc.) modified in order to optimize them relative to the system and materials parameters.
In yet another aspect of the invention, benefits are derived from the fast-speed singulation methods (such as sawing) of the assembled and encapsulated devices, and the lower costs of the molding compounds and methods (as compared to potting materials and methods).
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.